Single Event Upsets in SRAM FPGA based readout electronics for the Time Projection Chamber in the ALICE experiment

Abstract

Single Event Upsets in SRAM FPGA based readout electronics for the Time Projection Chamber in the ALICE experiment irradiation test results have been used to predict the single event upset rate expected during operation in the ALICE experiment. Due to the number of FPGAs utilized in the TPC front-end electronics, single event upsets can be a reliability concern. In order to reduce the probability of system malfunction, a reconfiguration solution was developed that enables the possibility to clear single event upsets in the configuration memory of the FPGA. Irradiation test results show that combined with additional system level mitigation techniques, this reconfiguration solution can be used to finally reduce the functional failure rate of the FPGA. Because irradiation testing can be time consuming, costly and sometimes even technically difficult, a software based fault injection solution has been implemented without any modification to the existing hardware setup. It provides an alternative and possibly systematic method of testing how a single event upset may impact the operation of the FPGA. Test results show good agreement with comparable irradiation test results. Finally physics based Monte Carlo simulations are discussed as an additional method to investigate single event upset in memory devices. A general methodology is presented and applied to the specific case study of the TPC front-end electronics FPGA.