| dc.description.abstract | The wide bandwidth in the unlicensed 60 GHz band enable short range wireless data transfer in the order of tens of gigabit per second. This, combined with the relatively low-cost, very high performance SiGe fabrication processes, has led to a feasibility study of a 60 GHz transceiver at Heidelberg University. Such a wireless system is useful in very many applications, and is proposed as the read-out of the future upgraded trackers in the ATLAS detector in the Large Hadron Collider. The work presented here is the design of the power amplifier block in the transceiver. The power amplifier design consists of three cascaded stages of common emitters, using the heterojunction bipolar transistors in the 0.13 µm SiGe BiCMOS process from IHP. Class AB operation ensures a good trade-off between efficiency and linearity. With load pull simulation, the output impedance was optimized for maximum output power. This was achieved without suffering from a bad output return loss and reflections, because conjugate matching was also attained at the output. Performance simulations yield a power gain of 21.5 dB, a bandwidth of 9 GHz and a peak power added efficiency of 19%. The output referred 1 dB compression point was simulated to 6.5 dBm, for which the amplifier consumes 24 mW. A layout of the power amplifier circuit measuring 0.15 square millimeters is proposed. Verification tests like electromagnetic simulation and corner and yield analysis remain, after which the presented block design can be implemented in the top level design of the transceiver chip. | en_US |
