Evaluation and design of readout electronics for electron and proton detectors
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Researchers at Birkeland center of space science have initiated a project where the precipitating flux of energetic electrons and protons into the middle atmosphere will be measured. An instrument will be attached to a low earth orbit (LEO), polar satellite. At the start of this thesis, only the radiation detectors were specified. It was also determined that the detector readings would be oversampled by an analog to digital converter (ADC), and processed on a field programmable gate array (FPGA). Finding an ADC that can be used in this project, and creating interfaces and an evaluation system to it are the main goals of this thesis. A block diagram overview is made for the entire measurement system. The discussion around this proved helpful to define tasks needed in this project, and it will continue to be helpful for future work. A potential candidate for an ADC is identified after an extensive search. Potential reliability concerns are discussed, as well as the analog signal processing that might be necessary with the ADC in question. FPGAs that are potential candidates for this project are considered. Digital design methods for ADC data acquisition and ADC control are discussed in relations to the project and the FPGA alternatives. All methods are at various levels realized and tested. A synthesizable VHDL model of the ADC is made to test the digital designs close to the real-life application. To test against the actual ADC, a testboard is made. This testboard also contains electronics for differential conversion, electronics that enable having multiple sample-clock sources, as well as voltage level mitigation circuitry. A VHDL testbench is made to verify the digital designs in the development phase. A system on chip (SoC) is made to interface with the ADC testboard. The functionality of the SoC includes setting various output data from the ADC and checking readout data automatically, accessing ADC configuration memory, testboard-component control, ADC sample-clock generation, “real-time” monitoring of readout data, and error tracking and error alerts for long term testing. The SoC is tested and verified in all design stages before implementation. A system is made where the SoC is internally connected to the ADC model. This is tested and verified in a computer-aided testbench in the pre-synthesis-, post-synthesis-, and post-layout- stage. After implementation, the SoC is tested in a physical, software-based testbench. A similar system is made where the signals between the digital designs and the model are looped back through I/Os on the FPGA. This is also tested in computeraided- and physical- testbenches. The testboard SoC is also tested and verified in a computer-aided testbench. The testboard is realized at a late stage in this thesis. It was not enough time to properly test the testboard SoC and testboard together. Some issues are found, but it is possible that the first version of the testboard is fully functional. If so, further testing can commence.