Low Power Giga Bit Transceiver (lpGBT) Test-Suite
Master thesis
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Date
2023-12-20Metadata
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- Master theses [170]
Abstract
The ALICE detector, one of the key instruments at CERN's LHC, is dedicated to capturing and measuring the properties of particles generated in high-energy particle collisions. To enhance its capabilities for studying these collisions, the ALICE detector is set to incorporate the FoCal sub-detector for the next experiment run. This sub-detector consists of various sensors for data collection, including pixel layers. UiB has taken the lead in incorporating these pixel layers, which are equipped with custom sensor chips designed to gather extensive data from particle collisions. A challenge lies in efficiently offloading this data from the sensors to servers for later analysis. This is particularly challenging due to the substantial volume of data and the impact the radioactive environment created by the collisions have on electronic components. To address this challenge, a comprehensive system is required, featuring custom-made components designed to withstand radiation near the sensors and commercially available components in radiation-free areas. Central to this data offloading process is the Versatile Link+ ecosystem, a set of components designed by CERN engineers to bridge these two environments. To successfully integrate these components with the pixel layers, a thorough understanding of their operation and utilization is crucial.
This thesis aims to explore and gain this understanding, encompassing the specifications crucial for both the pixel layers, and the Versatile Link+ ecosystem. Furthermore, it initiates the development of a test-suite for this ecosystem, serving as a practical platform for hands-on experience with its components. This test-suite holds the potential to contribute to the final design of the pixel layers readout system. The primary focus of this thesis has been on the development of FPGA designs responsible for managing communication with the lpGBT chip, the front-end component of the Versatile Link+ ecosystem. These FPGA designs play an important role in facilitating data exchange between the back-end and the front-end of the system, ensuring the establishment of a functional link. Extensive verification of the designs have been conducted through simulations, employing independent testbenches and a simulation platform developed by CERN for a complete Versatile Link+ ecosystem simulation.