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dc.contributor.authorImaña, José L.
dc.contributor.authorKaleyski, Nikolay Stoyanov
dc.contributor.authorBudaghyan, Lilya
dc.date.accessioned2024-05-02T12:02:32Z
dc.date.available2024-05-02T12:02:32Z
dc.date.created2023-11-02T09:38:31Z
dc.date.issued2023
dc.identifier.issn0141-9331
dc.identifier.urihttps://hdl.handle.net/11250/3128838
dc.description.abstractCryptographically strong functions used as S-boxes in block cyphers are fundamental for the cypher’s security. Their representation as lookup tables is possible for functions of small dimension. For larger dimensions, this is infeasible, especially if resources are limited. An alternative is representing the function as a polynomial over a finite field, and constructing a circuit evaluating this polynomial. We study how the choice of primitive polynomial affects the efficiency of hardware implementations. We take Dillon’s permutation on 6 bits (the only known permutation in even dimension from the cryptographically optimal Almost Perfect Nonlinear functions) as a relevant example, and present hardware architectures, polynomial representations and hardware theoretical complexities for all primitive polynomials of degree six. To compare the efficiency, we report on results obtained from FPGA (Field Programmable Gate Array) implementations. To the best of our knowledge, no similar study has been given in the literature. We observe that using the primitive trinomial 𝑦6 + 𝑦 + 1 reduces the number of 2-input XOR gates up to 11.7% and the number of XOR gates × Delay metrics up to 13.2% with respect to the worst-case implementation. Therefore, the choice of primitive polynomial can profoundly impact the efficiency of such an implementation, and should be carefully considered.en_US
dc.language.isoengen_US
dc.rightsNavngivelse 4.0 Internasjonal*
dc.rights.urihttp://creativecommons.org/licenses/by/4.0/deed.no*
dc.titleHardware architecture of Dillon's APN permutation for different primitive polynomialsen_US
dc.typeJournal articleen_US
dc.typePeer revieweden_US
dc.description.versionpublishedVersionen_US
dc.rights.holderCopyright 2023 The Author(s)en_US
dc.source.articlenumber104945en_US
cristin.ispublishedtrue
cristin.fulltextpostprint
cristin.qualitycode1
dc.identifier.doi10.1016/j.micpro.2023.104945
dc.identifier.cristin2191333
dc.source.journalMicroprocessors and Microsystems: Embedded Hardware Design (MICPRO)en_US
dc.identifier.citationMicroprocessors and Microsystems: Embedded Hardware Design (MICPRO). 2023, 103, 104945.en_US
dc.source.volume103en_US


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